The parts arrived and it was time to fit them and begin to test the power supply.
I am excited to share that I just received a BBC B home computer, a machine that has been on my wish list for over 25 years! This one came with a floppy drive and teletext controller. I also got about 30ish 5.25″ floppy disks.
I remember first using a BBC B computer in a friend’s house back in early 1984 and yes, he did have Elite (which was loaded from a cassette tape). It was the first time I had seen a 3D wireframe game on a computer. I remember thinking how wonderful it was and wondered what the future of computer games would be like, once technology got better.
While I was in third year in secondary school, I remember when the dean of my year asked what computers the school should get for the new computer room. At that point the school only had an Apple II computer. Some students were suggesting Commodore 64’s, while a few of us suggested the Beeb. I was very happy when a few months later we got told that we were getting Beeb’s.
I remember counting the days to the delivery date and feeling very sad (Sheldon sad) when I found out that we would not have the computers until after the Christmas holidays.
When we eventually got access to the computer lab, we found out that we had a network of 16 BBC B’s for workstations, a BBC Master with double drives for the server and another BBC B with an Epson Dot Matrix printer.
Many an evening was spent after school in the computer lab, writing programs in BASIC and learning my craft. At home I was using my Dad’s Epson HX-20 portable computer and friend’s computers. Although I was repairing faulty computers for friends and family, I didn’t have enough cash to buy my own.
So for a couple of years I wrote games for the Beeb, which my classmates would play when we had computer class. I always told myself that someday I would get a BBC B. When I left school in ’87 my dad got an IBM XT Clone for work. I started my collection of computers, which never included a BBC B until now.
So, here it is, an old yellowed BBC B computer. It has that old computer smell, so I hope that all is good inside, which may not be the case considering the age of this machine, so it looks like I’ll have to RetroBright the case, top and bottom.
I can’t wait any longer. I have the screwdriver out and it is time to open the computer to have a sneak peak inside.
At first glance it all looks good inside, although pretty dusty and in need of an Econet interface upgrade. Next step is to power up the computer to see if it works. This does not give the hoped for result – I get a constant tone from the computer speaker – the most common cause of this type of problem is faulty RAM.
This is not good, so before I do any more damage, I power off the computer and order a service manual for the Beeb which was a reproduction of the original manual. Further inspection of the computer shows up a damaged tube IDC connector.
I think I have a spare 40pin IDC connecter in stock, so this is on the list of things to fix for this computer.
The date stamp on the power supply puts a manufactured date of week 22 of 1982. This makes this computer 35 years old. I do check the voltages on the power supply and verify that I measure -5V and +5V, so it all looks good here, but I have no guarantee that it is a clean supply.
We can see from the main board that this is a revision 3 PCB.
After taking the board out and looking at the underside, I don’t see any bodge wires or hacks.
This is a good sign as it shows that no-one has tried to make any upgrades to this PCB. I hope that this means that the problems that exist are only minor issues.
One piece of test equipment that I had been missing for a while was a bench isolation transformer. This would have allowed me to perform tests and repairs that would protect me and the equipment being tested.
After looking around, I found it very difficult to find a device that met my requirements. Everything I found was too expensive or did not have what I wanted – a device with both voltage and current meters, with fuses on both the primary and secondary and an auto current trip on the input.
In the end I decided to build my own unit.
The core of the system was two identical transformers, wired back to back, to provide the isolation. These were sourced from some faulty UPSs, sourced on eBay. They were missing their batteries, but were working. I scrapped the UPSs and removed the parts that were worth keeping.
I recovered the current trip switch from an old Intermec 3400 Barcode Printer with a damaged chassis.
I was able to get a combination voltage/current/power meter on eBay, with a 6 week delivery from China.
The last few parts were a case and some IEC power connectors for both the input and the output, as well as fuses and fuse holders that I had in stock for many years.
The secondaries of the transformers were wired back to back – this provided dual isolation via the windings on both transformers. So when I tested it and connected the mains to the primary of the first transformer, I measured 230v AC on the primary of the second transformer. This proved that my theory worked, yay!
The meter gave me an indication when the device under test drew too much current, as well as showing the power draw. You may be thinking why did it show the current and voltage when the device was connected to the mains?
Well, I planned to connect the primary side of the isolation transformer into the output stage of a variac. A variac is a transformer with a variable output.
This allowed me to slowly increase the voltage to the device under test. I could see if the current draw was excessive and identify faulty equipment without having to connect the device to the mains and possibly blowing components, causing even more damage.
Note:Variacs are very handy devices that can be used to recondition old power supplies that may not have been used for a long period of time.
These two units coupled together provided me with a good environment to test devices for repair, while protecting myself and the customers device being repaired.
A female IEC connecter is used for the power output. This allowed me to have a selection of different leads that could plug in here.
Here is a photo of the Isolation Transformer connected to a Frequency Inverter. You can see that the meter is showing the output voltage, current that was being drawn as well as the power consumed.
The back of the unit just has a power input connection and an input fuse for protection.
Having decided that I was going to use an Atmel ATF22LV10C PLD to manage the address decoding for this project, I purchased a couple of these IC’s to try out. I was visited by Murphy’s Law. I found out that the new programmer wouldn’t program these ICs (although it listed these as supported ICs). After searching some forums, I found that I wasn’t the only person having a problem programming these ICs on this model of programmer. It turned out that the problem was down to the flash memory in the Atmel PLD. It required some special timing to program the ICs, which this programmer did not support.
So, my second attempt into this problem was to purchase some National GAL22V10 ICs (which my programmer said it also supported), but did I believe them? After testing them on my programmer and finding that they also didn’t work, I was getting very frustrated (serves me right for buying a cheap Chinese one). I really didn’t want to purchase a new programmer at that point, considering that it did work for other ICs.
Just to prove to myself that I was not losing it and that my grey matter was not shutting down, I tried some Lattice and National GAL16V8 ICs that I had in stock, and these programmed with no issue. I needed to rethink the address decoding, as I could use the working parts that I had to hand.
I was not happy to add two additional ICs into the project where I wanted to use one. Could I remove another IC to keep the chip count the same as before? After looking at the schematic it was simple to see that the /RE & /WE signal lines could be incorporated into one of the GALs.
If the first GAL contained the logic for these decoder lines (/RE & /WE) as well as the address decoding for the memory map, the second GAL could be used for the address decoding of the I/O.
This all seemed like a good plan, but NO, there was one sneaky problem that had now crept back in. The current consumption then increased dramatically in the system. Before we even measured this, I estimated that these GALs would burn about 40-80mA each (80 – 160mA in total). This blew the power budget that I wanted as a limit for the system.
As low power consumption was a key prerequisite for this project and as I then could not use the PLDs, I had to look back to using basic logic devices for managing the address decoding. It looked as if we would have to use some 74HC138s and 74HC139s. In the end the chip count increased.
That was a month’s work and planning that I wasn’t getting back.
All the memory devices require an active low control line and A15 will be high when the CPU is reset/starts. We can just use an inverter to get an active low signal from the A15 line which is high when the CPU starts. This is done by feeding A15 into a NAND gate 74HC00 (U4A), in an inverter configuration.
This active low A15 signal with A14 and A13, feed into a two to four line decoder 74HC139 (U5A), which allows us to cut the upper 32K memory space into 4 x 8K pages. Three of these pages can be used for our ROM memory which stores our software. The last 8K page can be used for future expansion, video memory and I/O.
This I/O control line can be fead into another NAND gate 74HC00 (U4B), with address line A9. This gives us a memory space of 512 bytes – it make better use of the memory space. We can feed this control line with A8 and A7 through A5, into a three to eight line decoder – 74HC138 (U10). This gives us 8 x 32 byte address blocks, which can be used for I/O devices such as RTC, UARTS, PIAs.
As we can see there are some unused memory spaces in the revised memory map. These can be used by other interfaces in the future.
So, after a couple of weeks since writing the first post about this Micro, I’m rethinking the address decoding and mapping of the same. Currently, address line A15 is being used to select between the lower 32K of memory and the upper 32K of memory. In the lower 32K of memory, I will page 32K block of RAM in and out, as needed. While the upper 32K of memory will be used for ROM and video RAM. I had previously suggested using a 3-8 line decoder to break up the upper 32K of memory into 4K chunks and then join a few of them to give 8K chunks. After a few days of writing the post about address decoding, I realised there were a few options available.
If I use a 2 to 4 line decoder (74HC139), I can use address lines A14 and A13 to break the upper 32K of memory into 4 x 8K blocks (which makes it easier for memory management). The upper 3 x 8K blocks can be used for firmware. I can potentially look at paging out one or two of these 8K blocks.
The lower 8K page can be sub divided into 4 x 2K blocks using another 2 to 4 line decoder (74HC139) on address lines A12 and A11. One of these 2K blocks can be used for basic video memory. If I add a second or third 2K block this would give 4K or 6K of video memory, which would suffice for a basic 40 column x 25 line or 80 column by 25 line display (with some basic colours and cursor functions).
The lower 2K block can be sub divided into 8 x 256 byte pages for I/O. This is still allot of wasted address space for I/O, so what can be done to be more efficient with the memory usage?
We can use a programmable logic device , a “PLD”, to manage the control logic for the I/O. This way we can re-program the PLD at a future date to incorporate any additional changes to the I/O that we may want.
Using an Atmel ATF22LV10C will give us up to 10 outputs each, which can be individually assigned to one or more addresses. With up to 12 address inputs, the PLD makes it easier to map the control lines required. The unused pins on this device will be brought out to a header in case we need to use these pins at a later date. This is a simpler solution to the multiple address decoders and additional logic ICs that potentially we were looking at.
When looking at the above revised memory map, we can see the I/O region is spread over 256 bytes of memory.
Years ago I used us a Hi-Lo Programmer that connected to my PC via an ISA card. This device was supplied with its own DOS program for taking Boolean logic and producing a map file which could be programmed into a PLD or a GAL. As I can’t use this anymore on modern PCs or a laptop, I need to find a more modern solution.
So I purchased a G540 programmer on eBay for very little money. The G540 was supplied with some adaptors for PLCC devices. A chip extractor was also supplied with this package. This programmer has a USB port, so it can connect to my laptop or desktop PC.
Atmel has a utility call WinCupl which allows you to write Boolean logic and create a map file which can be programmed into the 22LC10 PLD. I’ve never used this program before, so a little bit of study will be needed.